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Thursday, October 30 • 11:00 - 11:20
HPC - Low Latency Silicon Interconnect Proposed Specification

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This presentation will cover a proposed interconnect path for low latency multi processor energy efficient computing that will support up to exascale computing, code name LaserConnect. To accelerate time to market  LaserConnect 1.0 will be based on the  open multi vendor RapidIO 10xN (3.0) protocol leveraging the deployment attributes in over 100M production ports shipped into wireless networking, High Performance Embedded Computing, Space, Defence, Aerospace and Video applications.  It will benefit from many SoCs and interconnect devices and IP already being developed with RapidIO 10xN.  LaserConnect 2.0 will evolve from LaserConnect 1.0 for the specific needs of HPC, Supercomputing, High Performance Storage and financial trading and scale to higher bandwidths, and lower latencies.  LaserConnect will be focused on chip to chip, board to board, chassis to chassis and rack to rack for applications that are latency sensitive, but will work with Ethernet for Data Center spine scale out.

Thursday October 30, 2014 11:00 - 11:20
Curie École Polytechnique in Paris, France