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Friday, October 31 • 11:30 - 12:00
HPC - System on chip for HPC

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This talk will explore the benefits and tradeoffs with architecting a power efficient System on Chip (SoC) for HPC and comparing it to mainstream homogeneous multicore processors. Power efficiency drives the need for a heterogeneous compute architecture, with general purpose cores such as ARMs and compute focused elements such as DSPs or GPUs on the same device. The second component of the SoC is the integration of high speed IO such as SRIO and Ethernet, primarily for latency benefits and for further power and board are benefits


Friday October 31, 2014 11:30 - 12:00
Curie École Polytechnique in Paris, France

Attendees (1)